Increasing demand for computer system scalability (i.e., consistent price and performance and higher processor counts) combined with increases in performance of individual components continues to drive systems manufacturers to optimize core system architectures. One such systems manufacturer has introduced a server system that meets these demands for scalability with a family of application specific integrated circuits (“ASICs”) that provide scalability to tens or hundreds of processors, while maintaining a high degree of performance, reliability, and efficiency. The key ASIC in this system architecture is a cell controller (“CC”), which is a processor-I/O-memory interconnect and is responsible for communications and data transfers, cache coherency, and for providing an interface to other hierarchies of the memory subsystem.
In general, the CC comprises several major functional units, including one or more processor interfaces, memory units, I/O controllers, and external crossbar interfaces all interconnected via a central data path (“CDP”). One or more specialized performance counters, or performance monitors, are connected to the CDP and are useful in collecting data from the CDP for use in debugging and assessing the performance of the system of which the CC is a part. Currently, each of the performance counters is capable of collecting data from only one preselected portion of the CDP, such that the combination of all of the performance counters together can collect all of the data on the CDP. While this arrangement is useful in some situations, many situations exist in which it would be advantageous for more than one of the performance counters to access data from the same portion of the CDP in order to perform debugging operations. In this respect, to facilitate debugging it would be advantageous to be able to detect both the rising edges and falling edges of the accessed data. These applications are not supported by the state-of-the-art performance counters.